The present invention relates to methods of operating a memory device having a multi-level cell (MLC), and more particularly, to methods of reading and writing a spin transfer torque magnetic random access memory (STT-MRAM) device having an MLC array.
Spin transfer torque magnetic random access memory (STT-MRAM) is a new class of non-volatile memory, which can retain the stored information when powered off. An STT-MRAM device normally comprises an array of memory cells, each of which includes a magnetic memory element and a selection transistor coupled in series between appropriate electrodes. Upon application of an appropriate current to the magnetic memory element, the electrical resistance of the magnetic memory element would change accordingly, thereby switching the stored logic in the respective memory cell.
FIG. 1 is a schematic circuit diagram of a STT-MRAM device 30, which comprises a plurality of memory cells 32, each of the memory cells 32 including a selection transistor 34 coupled to a magnetic memory element 36; a plurality of parallel word lines 38 with each being coupled to a respective row of the selection transistors 34 in a first direction; and a plurality of parallel bit lines 40 with each being coupled to a respective row of the memory elements 36 in a second direction perpendicular to the first direction; and optionally a plurality of parallel source lines 42 with each being coupled to a respective row of the selection transistors 34 in the first or second direction.
The magnetic memory element 36 normally includes a magnetic reference layer and a magnetic free layer with an insulating electron tunnel junction layer interposed therebetween, thereby forming a magnetic tunneling junction (MTJ). An MTJ may have additional layers, such as magnetic pinned layer, seed layer, and magnetic pinning layer, to improve its performance. The magnetic reference layer has a fixed magnetization direction and may be anti-ferromagnetically exchange coupled to a magnetic pinned layer, which has a fixed but opposite or anti-parallel magnetization direction. Upon the application of an appropriate current through the MTJ, the magnetization direction of the magnetic free layer can be switched between two directions: parallel and anti-parallel with respect to the magnetization direction of the magnetic reference layer. The electron tunnel junction layer is normally made of an insulating material with a thickness ranging from a few to a few tens of angstroms. When the magnetization directions of the magnetic free and reference layers are substantially parallel, electrons polarized by the magnetic reference layer can tunnel through the insulating tunnel junction layer, thereby decreasing the electrical resistivity of the MTJ. Conversely, the electrical resistivity of the MTJ is high when the magnetization directions of the magnetic reference and free layers are substantially anti-parallel. The stored logic in the magnetic memory element can be switched by changing the magnetization direction of the magnetic free layer between parallel and anti-parallel with respect to the magnetization direction of the reference layer. Therefore, the MTJ has two stable resistance states that allow the MTJ to serve as a non-volatile memory element.
Based on the relative orientation between the magnetic reference and free layers and the magnetization directions thereof, a MTJ can be classified into one of two types: in-plane MTJ, the magnetization directions of which lie substantially within planes parallel to the same layers, or perpendicular MTJ, the magnetization directions of which are substantially perpendicular to the layer planes.
FIGS. 2A-2D illustrate operation of a conventional STT-MRAM cell including an in-plane MTJ memory element 50 coupled to a selection transistor 52 in series. The MTJ memory element 50 includes a magnetic reference layer 54 having an invariable in-plane magnetization direction 56 and a magnetic free layer 58 having a variable in-plane magnetization direction 60 or 66 with a tunnel junction layer 62 interposed therebetween. FIG. 2A shows with the magnetization direction 60 of the magnetic free layer 58 is parallel to the magnetization direction 56 of the magnetic reference layer 54, resulting in the MTJ memory element 50 in the low resistance state. During read operation, a read current 64 is passed through the MTJ memory element 50 and a corresponding potential of VLOW across the MTJ memory element 50 can be detected. FIG. 2B shows the read operation when the MTJ memory element 50 is in the high resistance state, which is characterized by the magnetic free layer 58 having a magnetization direction 66 that is anti-parallel or opposite to the magnetization direction 56 of the magnetic reference layer 54. A potential of VHIGH across the MTJ memory element 50 can be measured, wherein VHIGH is substantially higher than VLOW in order to distinguish the corresponding high and low resistance states.
FIG. 2C illustrates the write process for switching the resistance state of the MTJ memory element 50 from high to low. As electrons that pass through the magnetic reference layer 54 are being spin-polarized, the spin-polarized electrons exert a spin transfer torque on the magnetic free layer 58, causing the magnetization direction of the magnetic free layer 58 to switch from the anti-parallel 66 to parallel orientation 60 when the spin-polarized current or parallelizing current 68 exceeds a threshold level. It should be noted that the parallelizing write current 68 flows in the opposite direction as the electrons. Conversely, FIG. 2D illustrates the write process for switching the resistance state of the MTJ element 50 from low to high. As electrons pass through the magnetic free layer 58, the electrons with the same spin direction as that of the magnetization in the magnetic reference layer 54 pass into the magnetic reference layer 54 unimpeded. However, the electrons with the opposite spin direction are reflected back to the magnetic free layer 58 at the boundary between the tunnel junction layer 62 and the magnetic reference layer 54, causing the magnetization direction of the magnetic free layer 58 to switch from the parallel to anti-parallel orientation when the anti-parallelizing current 70 exceeds a threshold level.
FIGS. 3A-3D illustrate operation of a conventional STT-MRAM cell including a perpendicular MTJ memory element 80 coupled in series to a selection transistor 82. The MTJ memory element 80 includes a magnetic reference layer 84 having an invariable perpendicular magnetization direction 86 and a magnetic free layer 88 having a variable perpendicular magnetization direction 90 or 96 with a tunnel junction layer 92 interposed therebetween. The operation of the perpendicular MTJ memory element 80 as shown in FIGS. 3A-3D is substantially similar to that of the in-plane MTJ memory element 50 as illustrated in FIGS. 2A-2D and described above. FIGS. 3A and 3B shows the resistance state of the MTJ memory element 80 can be determined by passing a read current 94 therethrough. The resistance state can be switched from high to low by a parallelizing write current 98 flowing in the direction of the MTJ memory element 80 to the selection transistor 82 as illustrated in FIG. 3C. Conversely, FIG. 3D shows the resistance state can be switched from low to high by an anti-parallelizing write current 100 flowing in the opposite direction.
To be cost competitive, a small memory cell size and a memory cell capable of storing multiple bits of data are desired to yield maximum bits per die. Unlike the floating gate based flash memory, such as conventional NAND, which can be programmed to read 4 or more voltage levels, a single MTJ memory element only has two stable resistance states. Therefore, a conventional STT-MRAM device can only store 1 bit of data per cell, which is a disadvantage compared with other memory devices capable of storing multiple bits per cell.
Information relevant to attempts to address this issue can be found in U.S. Pat. Application Publication No. US 2012/0243311 A1 and U.S. Pat. Application Publication No. US 2012/0134200 A1, which disclose MTJ memory cells having two parallel MTJ memory elements coupled to a selection transistor. However, each one of these references suffers from one or more of the following disadvantages: the maximum number of memory elements per selection transistor is limited because of the read operation scheme employed and the parallel memory element layout is not space-efficient for small selection transistors.
For the foregoing reasons, there is a need for an MLC and a method for operating a space-efficient MLC cell.